1. Field of the Invention
The present invention relates to data driven type information processors, and particularly to a data driven type information processor to which an operation instruction capable of being processed in the processor is added, enhancing efficiency in accessing a data memory unit thereof.
2. Description of the Background Art
In a conventional von Neumann computer, various instructions are stored in advance as a program in a program memory, and addresses in the program memory are sequentially specified by a program counter, so that the instructions are sequentially read out, whereby the read instructions are executed.
A data driven type information processor is one of the non yon-Neumann computers which does not have a concept of sequential execution of instructions by a program counter. In such a data driven type information processor, architecture based on parallel processing of instructions is employed. In the data driven type information processor, an operation can be executed upon collection of data to be operated, and in the case of some data a plurality of operations are to be simultaneously executed, so that programs are executed in parallel according to a natural flow of the data. As a result, it is considered that time required for operations is considerably reduced.
FIG. 6 is a block diagram showing the structure of one example of a conventional data driven type information processor.
FIG. 7 is a diagram showing a field structure of a data packet to be processed in a conventional information processor and in one embodiment of the present invention.
The data packet shown in FIG. 7 includes a destination field F1, an instruction field F2, a first data field F3 and a second data field F4. Destination information is stored in the field F1, instruction information is stored in the field F2, and operand data is stored in the field F3 or F4.
The information processor shown in FIG. 6 includes a program storage unit 100 including a program memory, a paired data detecting unit 2 including a queuing memory, an operation processing unit 3, and an input/output control unit 4. The information processor further includes an external data memory device 10 externally provided. FIG. 8 is a diagram showing a part of a data flow program stored in the program memory of the program storage unit 100 of FIG. 6. FIG. 9 is a diagram showing a part of data stored in the queuing memory of the paired data detecting unit 2 of FIG. 6.
In the memory of the program storage unit 100, the data flow program PR shown in FIG. 8 is stored in advance. The data flow program PR includes a plurality of destination information and instruction information. The program storage unit 100 reads out subsequent destination information and subsequent instruction information from the program PR stored in the memory by addressing based on destination information stored in an input data packet, stores the read out subsequent destination information and subsequent instruction information in the destination field F1 and the instruction field F2 of the input data packet, respectively, and outputs the data packet. Instruction information stored in the program storage unit 100 is roughly divided into information concerning the operation processing unit 3, and information concerning the external data memory device 10. An arithmetic operation instruction, a logical operation instruction, a comparison operation instruction are listed as the former, and read out instructions ISEL, SSEL and CSEL, and writing instructions IREP, SREP and CREP are listed as the latter.
ISEL is an instruction for reading out integer type data of 4 bytes.
SSEL is an instruction for reading out short word type data of 2 bytes.
CSEL is an instruction for reading out character type data of 1 byte.
IREP is an instruction for writing integer type data of 4 bytes.
SREP is an instruction for writing short word type data of 2 bytes.
CREP is an instruction for writing character type data of 1 byte.
The paired data detecting unit 2 carries out queuing for a data packet provided from the program storage unit 100 in a queuing memory 2a of FIG. 9. When instruction information of the input data packet from unit 100 indicates a binomial instruction, queuing operand data stored in an addressing area in the queuing memory 2a based on the destination information of the input packet is read out. At this time, if queuing operand data has already stored in the addressing area as shown in 1 of FIG. 9, the queuing operand data is read out, and written in either of the field F3 or F4 in the input data packet, so that the input data packet storing two operand data is output. If queuing operand data is not stored in the addressing area of the memory 2a based on the destination information of the input data packet, operand data stored in the field F3 or F4 in the input data packet is written in the addressing area to wait for input of operand data to be paired therewith, as shown in 2 of FIG. 9. The paired data detecting unit 2 thus carries out paired data detecting processing, in which two different data packets having the same destination information are detected by the queuing memory 2a, operand data in one of these data packets (the contents of the first data field F3 in FIG. 7) is stored in the second data field F4 of the other data packet and the other data packet is output. The paired data detecting unit 2 receives a data packet provided from the program storage unit 100 to output the received data packet without any modification, when instruction information of the received packet indicates a monomial instruction.
The operation processing unit 3 receives a data packet provided from the paired data detecting unit 2, and decodes instruction information stored in the received data packet to apply operation processing to operand data stored in the field F3 or F4 of the received data packet according to the decoded instruction information. The result of the operation is stored into the first data field F3 in the received data packet, and the data packet is output.
The input/output control unit 4 has an input/output control function and an output control function. The input/output control function is to confluent in good order data packets supplied from the outside of the information processor or the operation processing unit 3 while temporarily storing them, and sequentially output the same. The output control function is to provide a data packet received from the operation processing unit 3 to any one of the program storage unit 100, the external data memory device 10 and the outside of the information processor, based on destination information stored in the data packet.
In a thus structured data driven type information processor, program data read out from program storage unit 100 continues circulating as a data packet through program storage unit 100.fwdarw.paired data detecting unit 2.fwdarw.operation processing unit 3.fwdarw.input/output control unit 4 .fwdarw.program storage unit 100, so that operation processing based on the data flow program PR stored in program storage unit 100 is performed.
The external data memory device 10 includes a data memory interface 11 and a data memory unit 12. The data memory unit 12 stores data to be subjected to operation processing in the data driven type information processor. The data memory interface 11 accesses data memory unit 12 based on instruction information and operand the data stored in a data packet supplied through the input/output control unit 4. Data stored in the data memory unit is hereinafter referred to as memory data. The external data memory device 10 operates based on data stored in a data packet supplied after circulation through program storage unit 100.fwdarw.paired data detecting unit 2.fwdarw.operation processing unit 3.fwdarw.input/output control unit 4. Specifically, when the data memory interface 11 receives a packet from the input/output control unit 4, instruction information stored in the input packet is decoded, determining whether data is to be read out from the memory unit 12, or to be written into the memory unit 12. When the instruction information is one of the read out instructions described above (ISEL, SSEL and CSEL), the interface 11 addresses the memory unit 12 based on operand data (address data) stored in the field F3 of the received packet to read out memory data stored in the addressing area. The read out memory data is stored in the data field F3 of the received packet, and the received packet is applied to the input/output control unit 4. When the decoded instruction information is one of the writing instructions described above (IREP, SREP and CREP), the interface 11 addresses the data memory unit 12 based on operand data (address data) stored in the field F3 of the received packet to write operand data (data to be written) stored in the field F4 of the received packet into the addressing area.
In the instructions concerning external data memory device 10 in the conventional driven type information processor described above, an instruction for applying a designated address and designated data, and if memory data stored in an addressing area based on the designated address is larger than the designated data, then writing the designated data in the addressing area and providing 1, otherwise providing 0 without writing the data therein, and an instruction for applying a designated address and designated data, and if memory data stored in an addressing area based on the designated address is smaller than the designated data, then writing the designated data in the addressing area and providing 1, otherwise providing 0 without writing the data therein are not included. Hereinafter, these instructions are referred to as "comparison and replacement instructions", and processing performed according to these instructions is referred to as "comparison and replacement processing".
In carrying out "comparison and replacement processing" in the conventional data driven type information processor described above, the problem arises that numerous steps in the program concerning this processing prevents efficient processing in the information processor. This problem will now be described.
FIG. 10 is a data flow chart showing a conventional processing for a comparison and replacement instruction.
In the comparison and replacement processing shown in FIG. 10, the procedure for processing the instruction "apply a designated address and designated data, and if memory data stored in an addressing area based on the designated address is larger than the designated data, then write the designated data into the addressing area to output 1, otherwise output 0 without writing the data therein" is shown. Pentagonal symbols and circular symbols in FIG. 10 are termed nodes, in which input/output ports, operation instructions and the like are described. Node numbers #1-#6 are attached to respective nodes. The node numbers denote destination information, and the number of the node numbers is equal to the number of steps for the program stored in program storage unit 100. An operation instruction "&gt;" is a logical operation instruction to compare left input data coming from the left of the node in which the instruction is described and right input data coming from the right of the node, and when: the left input data&gt;the right input data, then output a true value "1", otherwise output a false value "0". An operation instruction "tg" is an operation instruction to hold and provide left input data if right input data is true, and erase the input data if the right input data is false. An operation instruction "fg" is an operation instruction to hold and provide left input data if right input data is false, and erase the input data if the right input data is true. An operation instruction "sync" is an operation instruction to synchronize left input data with right input data, and hold and output the same. As shown in FIG. 10, the operation instructions shown in #1-#6 are assembled to be an instruction group C. The operation instructions described in the nodes #1-#6 shown in FIG. 10 are paired with corresponding destination information #1-#6, respectively, to be stored in program storage unit 100 in advance.
The operation of the data driven type information processor of FIG. 6 in accordance with the data flow graph shown in FIG. 10 will now be described.
In operation, as shown in FIG. 10, the information processor receives a data packet P10 storing address data "pos" (designated address) and a data packet P11 storing write data "val" (designated data) to be written in an area of data memory unit 12 addressed by the address data "pos". Both of the data packets are processed in parallel in each unit of the data driven type information processor while program data stored in program storage unit 100 is read out. In other words, the operation processing in each node within the instruction group C proceeds through parallel execution of the instruction of each node in the instruction group C of FIG. 10. After the operation processing in the instruction group C, a data packet P12 storing comparison and replacement processing result data X (0 or 1) is obtained at an output node.
In the "comparison and replacement processing" in the conventional data driven type information processor, since at least six instruction nodes (program steps of a data flow program) are required as shown in FIG. 10, for example, the problem of preventing utilization efficiency of a memory in program storage unit 100 arises.
Moreover, in parallel execution of the "comparison and replacement processing" for the identical address of data memory unit 12, data stored in an addressing area of data memory unit 12 based on the address data "pos" tends to change during a period from execution of the instruction "isel" (node of #1) through execution of the instruction "irep" (node of #5), which prevents the parallel execution of the "comparison and replacement processing". Therefore, parallelism in operation processing which is characteristic of the data driven type information processor is impaired, so that the problem arises that the speed of operation processing in the information processor is considerably reduced in execution of the "comparison and replacement processing".